1. Field of the Invention
This invention relates generally to the structure and fabrication process of a trenched DMOS power device. More particularly, this invention relates to a novel trenched DMOS device structure and fabrication process with double gate-oxide structure to reduce the gate/drain capacitance. The switching speed of the trenched DMOS device is improved without degrading the breakdown voltage. Also, a low threshold voltage is maintained by controlling the thickness of a thin-gate-oxide layer. Furthermore, the drain-to-source resistance is decreased by forming a high-dopant-concentration N+ buried-region without significantly increasing the drain-to-gate capacitance.
2. Description of the Prior Art
Several difficulties are faced by those involved in the technology to further increase the cell density of a power DMOS transistor in order to achieve a lower on resistance and meanwhile attempting to increase the DMOS switching speed.
FIG. 1 shows a DMOS prior art DMOS trench device 10 supported on a N+ substrate and an N-epitaxial layer. The DMOS device 10 includes trenched-gates 30 formed in the trenches filled with polysilicon and surrounded by body regions 20 and covered by an insulation layer 45. Each transistor cell further includes a N+ source region encompassed in the body region 20 disposed near the top surface of the substrate and right next to the trenched gates 30. The body region 20 further includes a high concentration P+ body dopant region 60 for reducing the contact resistance with the source contact metal 70. The source contact metal 70 contact the source regions 40 through openings in the insulation layer 45. The body regions 20 are formed with a depth less than the depth of the trenched-gate 30. The gate oxide uniformly grows along the trench sidewall. However, the device now faces the difficulty of increasing gate/drain capacitance as cell density increases. Moreover, early breakdown near the bottom of the trenched gates becomes a design concern if the gate oxide is not thick enough. Due to this limitation, a higher cell density of the DMOS power device with low gate/drain capacitance cannot be easily achieved. A conventional method is to increase the thickness of the gate oxide layer near. However, a gate-oxide layer with greater thickness will often affect the threshold voltage.
Therefore, a need still exits in the art of power device fabrication, particularly for trenched DMOS design and fabrication, to provide a structure and fabrication process that would resolve these difficulties. More specifically, it is preferably that a transistor with a high cell density can be produced with effective prevention against early breakdown without increasing the device threshold voltage. It is further desirable to reduce the gate charges between gate/drain such that the device switching speed can be improved.